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16Mb: 1 Meg x 16 Async/Page/Burst CellularRAM 1.0 Memory
Configuration Registers
Output Impedance (BCR[5]) Default = Outputs Use Full Drive Strength
The output driver strength can be altered to adjust for different data bus loading
scenarios. The reduced-strength option should be more than adequate in stacked chip
(Flash + CellularRAM) environments when there is a dedicated memory bus. The reduced-
drive-strength option is included to minimize noise generated on the data bus during
READ operations. Normal output impedance should be selected when using a discrete
CellularRAM device in a more heavily loaded data bus environment. Partial drive is
approximately one-quarter full drive strength. Outputs are configured at full drive
strength during testing.
WAIT Configuration (BCR[8]) Default = WAIT Transitions One Clock Before Data Valid/Invalid
The WAIT configuration bit is used to determine when WAIT transitions between the
asserted and the de-asserted state with respect to valid data presented on the data bus.
The memory controller will use the WAIT signal to coordinate data transfer during
synchronous READ and WRITE operations. When BCR[8] = 0, data will be valid or invalid
on the clock edge immediately after WAIT transitions to the de-asserted or asserted
state, respectively (see Figures 18 and 20). When BCR[8] = 1, the WAIT signal transitions
one clock period prior to the data bus going valid or invalid (see Figures 19 and 20).
WAIT Polarity (BCR[10]) Default = WAIT Active HIGH
The WAIT polarity bit indicates whether an asserted WAIT output should be HIGH or
LOW. This bit will determine whether the WAIT signal requires a pull-up or pull-down
resistor to maintain the de-asserted state.
Figure 18:
WAIT Configuration (BCR[8] = 0)
C LK
WAIT
DQ[15:0]
High-Z
Data[0]
Data[1]
Data imme d iately vali d (or invali d )
Note:
Data valid/invalid immediately after WAIT transitions (BCR[8] = 0). See Figure 20 on
page 26.
Figure 19:
WAIT Configuration (BCR[8] = 1)
C LK
WAIT
D[15:0]
High-Z
Data[0]
Data vali d (or invali d ) after one c lo c k d elay
Note:
Valid/invalid data delayed for one clock after WAIT transitions (BCR[8] = 1). See Figure 20
on page 26.
PDF: 09005aef81cb58ed/Source: 09005aef81c7a667
16mb_burst_cr1_0_p23z_2.fm - Rev. H 4/08 EN
25
Micron Technology, Inc., reserves the right to change products or specifications without notice.
?2005 Micron Technology, Inc. All rights reserved.
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